1. Field of the Invention
The present invention relates generally to level determining circuits, and more particularly, to a general purpose type of level determining circuit suitable for being implemented as a semiconductor integrated circuit.
2. Description of the Background Art
General purpose level determining circuits with wide range of applicability have been implemented so far as semiconductor integrated circuits. As an example of such level determining circuits, there exists one which comprises an input terminal and first and second output terminals for generating an output signal at the first or second output terminal according to the level of an input signal. Such a level determining circuit is used, for example, to perform balance control by determining the respective levels of L and R signals in a balance adjusting circuit of a stereo system.
FIG. 1 is a circuit diagram showing an example of such conventional level determining circuits. Basically, the illustrated circuit determines the level of an input signal for operating in such a manner that it generates a first output signal at a first output terminal if the level is higher than a predetermined reference value, or generates a second output signal at a second output terminal if the level is lower than the predetermined reference value.
Referring to FIG. 1, input signal is applied to a non-inverted input terminal of a comparing portion 1 through a terminal 19 and a predetermined reference voltage is applied to an inverted input terminal thereof.
When an input signal at a higher level than the reference voltage applied to the inverted input terminal is applied to the non-inverted input terminal of the comparing portion 1, a positive output signal is generated from the comparing portion 1. This positive output signal is supplied to a first output terminal 11 through a diode 2, a resistance 5 and a switch 10.
Meanwhile, when an input signal at a lower level than the preceding reference voltage is applied to the non-inverted input terminal of the comparing portion 1, a negative output signal is generated from the comparing portion 1. This negative output signal is supplied to a second output terminal 12 through a diode 3 and a resistance 8.
Operation of the level determining circuit shown in FIG. 1 will be described in more detail below. Now, assuming that input signal V.sub.IN is greater than reference voltage V.sub.REF, with V.sub.IN as an input signal and V.sub.REF as a reference voltage of a reference voltage source 13, the level V.sub.1 of the positive output signal generated at the first output terminal 11 is defined by the following expression: ##EQU1## where R.sub.1 through R.sub.6 represent resistance values of the resistances 4 through 9, respectively.
On the other hand, assuming that input signal V.sub.IN is smaller than reference voltage V.sub.REF, the level V.sub.2 of the negative output signal generated at the second output terminal 12 is defined by the following expression: ##EQU2##
Therefore, the circuit shown in FIG. 1 operates as a level determining circuit which generates an output signal at the first output terminal 11 or the second output terminal 12 according to the level of an input signal.
In addition, the following relation should be established in order to ensure equal bias voltages of the diodes 2 and 3. EQU R.sub.2 +R.sub.3 =R.sub.5 +R.sub.6
In such a level determining circuit as described in the above, it may be required that either one of the output signals supplied at the first and second output terminals should be disconnected by means of a switch for various reasons. For example, the conventional level determining circuit shown in FIG. 1 is constructed in such a manner that supply of the first output signal to the first output terminal 11 can be disconnected if required.
However, in a conventional example as shown in FIG. 1, if the switch 10 disconnects supply of the first output signal, impedance on the side of the switch 10 with respect to the node between resistances 5 and 6 will change corresponding to the opening of the switch 10 which results in fluctuation of the reference voltage applied to the negative input terminal of the comparing portion 1. Thus, there has been a problem that such switching of the switch 10 prevents precise determination about the level of an input signal.